1. Field of the Invention
The present invention generally relates to a data processing device and, more particularly, to a data processing device, a data processing method and a data processing system.
2. Description of the Related Art
FIG. 1 is an illustration of a structure of a conventional processing system comprising a Synchronized Dynamic Random Access Memory (SDRAM) capable of reading and writing data at high speed, and an SDRAM bus used to access the SDRAM.
As shown in FIG. 1, the conventional processing system comprises a first central processing unit (CPU) 1, a second central processing unit (CPU) 3, an SDRAM 5, a Read-Only Memory (ROM) 7, a Random Access Memory (RAM) 9, an input-output buffer (I/O) 11, an SDRAM bus 13 and a general purpose bus 15.
The SDRAM bus 13 and the general purpose bus 15 each connect the first CPU 1 and the second CPU 3. The ROM 7, the RAM 9 and the I/O 11, all of which are resources, are connected to the general purpose bus 15, and are accessible by both the first and second CPUs 1 and 3. The SDRAM 5 is connected to the SDRAM bus 13, and is accessible by both the first and second CPUs 1 and 3.
However, the conventional processing system involves the following problems.
Generally, a CPU exchanging data via the SDRAM bus 13 has complicated functions and many terminals, making the CPU costly. Also, as shown in FIG. 1, in order that a plurality of CPUs (the first and second CPUs 1 and 3, for example) use a memory area comprising one SDRAM 5 or a plurality of SDRAMs, the SDRAM bus 13 has to be connected to the SDRAM(s) and a plurality of the CPUs, complicating the transmission path of the SDRAM bus 13.
Further, although the SDRAM 5 is capable of operating at a high speed of an operating frequency equal to or more than 100 MHz, the above-mentioned complicated transmission path of the SDRAM bus 13 leads to decreasing the operating frequency.
Also, in order that a plurality of CPUs use a memory area in the SDRAM with using the SDRAM bus, arbitrating operations to decide which of the CPUs uses the SDRAM bus with priority need to be conducted between the CPUs. Therefore, means (comprising software and/or hardware) for controlling a plurality of the CPUs is complicated.